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lnk623-626 linkswitch-cv family www.powerint.com september 2009 energy-effi cient, off-line switcher with accurate primary-side constant-voltage (cv) control ? output power table product 3 230 vac 15% 85-265 vac adapter 1 peak or open frame 2 adapter 1 peak or open frame 2 lnk623pg/dg 6.5 w 9 w 5.0 w 6 w lnk624pg/dg 7 w 11 w 5.5 w 6.5 w lnk625pg/dg 8 w 13.5 w 6.5 w 8 w lnk626pg/dg 10.5 w 17 w 8.5 w 10 w table 1. output power table. based on 5 v output. notes: 1. minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 c ambient. 2. maximum practical continuous power in an open frame design with adequate heatsinking, measured at 50 c ambient (see key application considerations section for more information). 3. packages: p: dip-8c, d: so-8c. product highlights dramatically simpli? es cv converters ? eliminates optocoupler and all secondary cv control circuitry ? eliminates bias winding supply C ic is self biasing advanced performance features ? compensates for external component temperature variations ? very tight ic parameter tolerances using proprietary trimming technology ? continuous and/or discontinuous mode operation for design ? exibility ? frequency jittering greatly reduces emi ? lter cost ? even tighter output tolerances achievable with external resistor selection/trimming advanced protection/safety features ? auto-restart protection reduces delivered power by >95% for output short circuit and all control loop faults (open and shorted components) ? hysteretic thermal shutdown C automatic recovery reduces power supply returns from the ? eld ? meets hv creepage requirements between drain and all other pins, both on the pcb and at the package ecosmart ? C energy ef? cient ? no-load consumption <200 mw at 230 vac and down to below 70 mw with optional external bias ? easily meets all global energy ef? ciency regulations with no added components ? on/off control provides constant ef? ciency down to very light loads C ideal for mandatory eisa and energy star 2.0 regulations ? no primary or secondary current sense resistors C maximizes ef? ciency green package ? halogen free and rohs compliant package applications ? dvd/stb ? adapters ? standby and auxiliary supplies ? home appliances, white goods and consumer electronics ? industrial controls description the linkswitch-cv dramatically simpli?es low power, constant voltage (cv) converter design through a revolutionary control technique which eliminates the need for both an optocoupler and secondary cv control circuitry while providing very tight output voltage regulation. the combination of proprietary ic trimming and e-shield? transformer construction techniques enables clampless? designs with the linkswitch-cv lnk623/4. figure 1. t ypical application schematic (a) and output characteristic envelope (b). *optional with lnk623-624pg/dg. (see key application considerations section for clamp and other external circuit design considerations). linkswitch-cv * wide range hv dc input pi-5195-080808 d s fb bp (a) typical application schematic (b) output characteristic linkswitch-cv provides excellent cross-regulation for multiple- output ?yback applications such as dvds and stbs. a 700 v power mosfet and on/off control state machine, self-biasing, frequency jittering, cycle-by-cycle current limit, and hysteretic thermal shutdown circuitry are all incorporated onto one ic. i o v o 5% auto-restart pi-5196-080408 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 2 lnk623-626 www.powerint.com pin functional description drain (d) pin: this pin is the power mosfet drain connection. it provides internal operating current for both start-up and steady-state operation. bypass (bp) pin: this pin is the connection point for an external bypass capacitor for the internally generated 6 v supply. feedback (fb) pin: during normal operation, switching of the power mosfet is controlled by this pin. this pin senses the ac voltage on the bias winding. this control input regulates the output voltage based on the ? yback voltage of the bias winding. source (s) pin: this pin is internally connected to the output mosfet source for high voltage power and control circuit common returns. figure 2 functional block diagram. figure 3. pin con? guration. pi-51 9 7-110408 source (s) leading edge blanking + - + - + - drain (d) bypass (bp) feedback (fb) source (s) fb out reset 6 v 5 v t sample-out v ilimit i lim v th v ilimit 6.5 v drive i lim dc max t sample-out dc max fb current limit comparator state machine sample delay thermal shutdown oscillator fault auto-restart open-loop dq regulator 6 v pi-51 9 8-071608 3a 3b d s bp s s fb p package (dip-8c) d package (so-8c) 8 5 7 1 4 2 s 6 d s bp s s fb 8 5 7 1 4 2 s 6 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 3 lnk623-626 www.powerint.com linkswitch-cv functional description the linkswitch-cv combines a high voltage power mosfet switch with a power supply controller in one device. similar to the linkswitch-lp and tinyswitch-iii it uses on/off control to regulate the output voltage. the linkswitch-cv controller consists of an oscillator, feedback (sense and logic) circuit, 6 v regulator, over-temperature protection, frequency jittering, current limit circuit, leading-edge blanking, and on/off state machine for cv control. constant voltage (cv) operation the controller regulates the feedback pin voltage to remain at v fbth using an on/off state-machine. the feedback pin voltage is sampled 2.5 s after the turn-off of the high voltage switch. at light loads the current limit is also reduced to decrease the transformer ? ux density. auto-restart and open-loop protection in the event of a fault condition such as an output short or an open loop condition the linkswitch-cv enters into an appropriate protection mode as described below. in the event the feedback pin voltage during the flyback period falls below v fbth -0.3 v before the feedback pin sampling delay (~2.5 s) for a duration in excess of 200 ms (auto-restart on- time (t ar-on ) the converter enters into auto-restart, wherein the power mosfet is disabled for 2.5 seconds (~8% auto-restart duty cycle). the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. in addition to the conditions for auto-restart described above, if the sensed feedback pin current during the forward period of the conduction cycle (switch on time) falls below 120 a, the converter annunciates this as an open-loop condition (top resistor in potential divider is open or missing) and reduces the auto-restart time from 200 ms to approximately 6 clock cycles (90 s), whilst keeping the disable period of 2.5 seconds. this effectively reduces the auto-restart duty cycle to less than 0.01%. over-temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is set at 142 c typical with a 60 c hysteresis. when the die temperature rises above this threshold (142 c) the power mosfet is disabled and remains disabled until the die temperature falls by 60 c, at which point the mosfet is re-enabled. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of that cycle. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and recti? er reverse recovery time will not cause premature termination of the mosfet conduction. 6.0 v regulator the 6 v regulator charges the bypass capacitor connected to the bypass pin to 6 v by drawing a current from the voltage on the drain, whenever the mosfet is off. the bypass pin is the internal supply voltage node. when the mosfet is on, the device runs off of the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows the linkswitch-cv to operate continuously from the current drawn from the drain pin. a bypass capacitor value of 1 f is suf? cient for both high frequency decoupling and energy storage. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 4 lnk623-626 www.powerint.com applications example circuit description this circuit is con? gured as a three output, primary-side regulated ? yback power supply utilizing the lnk626pg. it can deliver 7 w continuously and 10 w peak (thermally limited) from an universal input voltage range (85 C 265 vac). ef? ciency is >67% at 115 vac/230 vac and no-load input power is <140 mw at 230 vac. input filter ac input power is recti? ed by diodes d1 through d4. the recti? ed dc is ? ltered by the bulk storage capacitors c1 and c2. inductor l1, l2, c1 and c2 form a pi () ? lter, which attenuates conducted differential-mode emi noise. this con? guration along with power integrations transformer e-shield ? technology allow this design to meet emi standard en55022 class b with good margin without requiring a y capacitor. fuse f1 provides protection against catastrophic failure. negative temperature coef? cient thermistor rt1 limits the inrush current when ac is ? rst applied to below the maximum rating of diodes d1 through d4. metal oxide varistor rv1 clamps the ac input during differential line transients, protecting the input components and maintaining the peak drain voltage of u1 below its 700 v bv dss rating. for differential surge levels at or below 2 kv this component may be omitted. lnk626 primary the lnk626pg device (u1) incorporates the power switching device, oscillator, cv control engine, startup, and protection functions. the integrated 700 v mosfet provides a large drain voltage margin in universal input ac applications, increasing reliability and also reducing the output diode voltage stress by allowing a greater transformer turns ratio. the device can be completely self-powered from the bypass pin and decoupling capacitor c4. in this design a bias circuit (d6, c6 and r4) was added to reduce no load input power below 140 mw. the recti? ed and ? ltered input voltage is applied to one side of the primary winding of t1. the other side of the transformers primary winding is driven by the integrated mosfet in u1. the leakage inductance drain voltage spike is limited by the clamp circuit d5, r1, r2, c3 and vr1. the zener bleed clamp arrangement was selected for lowest no-load input power but in applications where higher no-load input power is acceptable vr1 may be omitted and the value of r1 increased to form a standard rcd clamp. output recti? cation the secondaries of the transformer are recti? ed by d7, d8 and d9. a schottky barrier type was used for the main 5 v output for higher ef? ciency. the +12 v and -22 v outputs use an ultrafast recti? er diode. the main output is post ? ltered by l3 and c10 to remove switching frequency ripple. resistors r7, r8 and r9 provide a preload to maintain the output voltages within their respective limits when unloaded. to reduce high frequency ringing and associated radiated emi an rc snubber formed by r10 and c13 was added across d7. figure 4. 7 w (10 w peak) multiple output flyback converter for dvd applications with primary sensed feedback. pi-5205-102208 d s fb bp r3 6.34 k 7 1% c13 270 pf r6 4.02 k 7 1% r1 5.1 k 7 1/8 w r2 390 7 r4 6.2 k 7 c4 1 m f 50 v c5 680 pf 50 v c8 1000 m f 10 v c10 470 m f 10 v c11 47 m f 50 v c9 47 m f 25 v c6 10 m f 50 v r5 47 k 7 1/8 w u1 lnk626pg linkswitch-cv d8 uf4003 d7 sb540 d6 1n4148 d9 uf4003 r9 39 k 7 1/8 w r8 24 k 7 1/8 w r7 510 7 1/8 w t1 eel19 16 7 11 8,9,10 12 5 4 2 3 c1 22 m f 400 v c2 22 m f 400 v c3 820 pf 1 kv f1 3.15 a rt1 10 7 8 5 - 265 vac l n d1 fr106 d2 fr106 vr1 1n5272b d5 1n4007 d3 1n4007 d4 1n4007 l1 3.5 7.6 mm ferrite bead l2 680 uh l3 10 m h 12 v, 0.1 a 5 v, 1.7 a rtn -22 v, 15 ma rv1 275 v r10 47 7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 5 lnk623-626 www.powerint.com output regulation the lnk626 regulates the output using on/off control, enabling or disabling switching cycles based on the sampled voltage on the feedback pin. the output voltage is sensed using a primary referenced winding on transformer t1 eliminating the need for an optocoupler and a secondary sense circuit. the resistor divider formed by r3 and r6 feeds the winding voltage into u1. standard 1% resistor values were used to center the nominal output voltages. resistor r5 and c5 reduce pulse grouping by creating an offset voltage that is proportional to the number of consecutive enabled switching cycles. key application considerations output power table the data sheet maximum output power table (table 1) represents the maximum practical continuous output power level that can be obtained in a flyback converter under the following assumed conditions: 1. the minimum dc input voltage is 100 v or higher at 90 vac input. the value of the input capacitance should be large enough to meet these criteria for ac input designs. 2. secondary output of 5 v with a schottky recti? er diode. 3. assumed ef? ciency of 80%. 4. continuous conduction mode operation (k p = 0.4). 5. re? ected output voltage (v or ) of 110 v. 6. the part is board mounted with source pins soldered to a suf? cient area of copper to keep the source pin tempera- ture at or below 110 c for p package and 100 c for d packaged devices. 7. ambient temperature of 50 c for open frame designs and an internal enclosure temperature of 60 c for adapter designs. note: higher output power are achievable if the ef? ciency is higher than 80%, typically for high output voltage designs. bypass pin capacitor a 1 f bypass pin capacitor (c4) is recommended. the capacitor voltage rating should be equal to or greater than 6.8 v. the capacitors dielectric material is not important. the capacitor must be physically located close to the linkswitch-cv bypass pin. circuit board layout linkswitch-cv is a highly integrated power supply solution that integrates on a single die, both the controller and the high voltage mosfet. the presence of high switching currents and voltages together with analog signals makes it especially important to follow good pcb design practice to ensure stable and trouble free operation of the power supply. when designing a board for the linkswitch-cv based power supply, it is important to follow the following guidelines: single point grounding use a single point (kelvin) connection at the negative terminal of the input ? lter capacitor for the linkswitch-cv source pin and bias winding return. this improves surge capabilities by returning surge currents from the bias winding directly to the input ? lter capacitor. bypass capacitor the bypass pin capacitor should be located as close as possible to the source and bypass pins. feedback resistors place the feedback resistors directly at the feedback pin of the linkswitch-cv device. this minimizes noise coupling. thermal considerations the copper area connected to the source pins provide the linkswitch-cv heat sink. a rule of thumb estimate is that the linkswitch-cv will dissipate 10% of the output power. provide enough copper area to keep the source pin temperature below 110 c to provide margin for part to part r ds(on) variation. secondary loop area to minimize leakage inductance and emi, the area of the loop connecting the secondary winding, the output diode and the output ? lter capacitor should be minimized. in addition, suf? cient copper area should be provided at the anode and cathode terminal of the diode for heatsinking. a larger area is preferred at the quiet cathode terminal. a large anode area can increase high frequency radiated emi. electrostatic discharge spark gap in chargers and adapters esd discharges may be applied to the output of the supply. in these applications the addition of a spark gap is recommended. a trace is placed along the isolation barrier to form one electrode of a spark gap. the other electrode, on the secondary side, is formed by the output return node. the arrangement directs esd energy from the secondary to the primary side ac input. a 10 mil gap is placed near the ac input. the gap decouples any noise picked up on the spark gap trace to the ac input. the trace from the ac input to the spark gap electrode should be spaced away from other traces to prevent unwanted arcing occurring and possible circuit damage. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 6 lnk623-626 www.powerint.com figure 5. pcb layout example. figure 6. schematic representation of recommended layout without external bias. figure 7. schematic representation of recommended layout with external bias. + - ac in pi-5269-122408 y1- capacitor (optional) isolation barrier transformer t1 output rectifiers primary side secondary side r1 jp1 j1 c1 r3 r4 c12 r10 d9 c11 c13 d7 c9 r9 r8 d8 16 r7 c8 l3 c10 c2 r2 c3 d1 d3 d5 vr1 d6 c6 r6 r5 c5 c4 d4 rv1 f1 d2 rt1 l2 l1 j2 input filter capacitor drain trace area miniminzed clamp components copper area maximized for heatsinking dc outputs esd spark gap bypass capacitor close to device feedback resistors close to device 10 mil gap u1 s fb bp d s s s output filter capacitor pi-5265-110308 kelvin connection at source pin, no power currents in signal traces minimize fb pin node area clamp d s fb bp b+ pri rtn bias currents return to bulk capacitor pi-5266-110308 kelvin connection at source pin, no power currents in signal traces bias currents return to bulk capacitor small fb pin node area bias resistor clamp d s fb bp pri rtn b+ www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 7 lnk623-626 www.powerint.com figure 8. schematic representation of electrical impact of improper layout. pi-5267-111008 bias winding currents flow in signal source traces voltage drops across trace impedance may cause degraded performance power currents flow in signal source trace line surge currents can flow through device drain trace in close proximity of feedback trace will couple noise into feedback signal b+ pri rtn clamp d s fb bp $ v s isource trace impedance www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 8 lnk623-626 www.powerint.com drain clamp recommended clamp circuits components r1, r2, c3, vr1 and d5 in ? gure 4 comprise the clamp. this circuit is preferred when the primary leakage inductance is greater than 125 h to reduce drain voltage overshoot or ringing present on the feedback winding. for best output regulation, the feedback voltage must settle to within 1% at 2.1 s from the turn off of the primary mosfet. this requires careful selection of the clamp circuit components. the voltage of vr1 is selected to be ~20% above the re? ected output voltage (v or ). this is to clip any turn off spike on the drain but avoid conduction during the ? yback voltage interval when the output diode is conducting. the value of r1 should be the largest value that results in acceptable settling of the feedback pin voltage and peak drain voltage. making r1 too large will increase the discharge time of c3 and degrade regulation. resistor r2 dampens the leakage inductance ring. the value must be large enough to dampen the ring in the required time but must not be too large to cause the drain voltage to exceed 680 v. if the primary leakage inductance is less than 125 h, vr1 can be eliminated and the value of r1 increased. a value of 470 k with an 820 pf capacitor is a recommended starting point. verify that the peak drain voltage is less than 680 v under all line and load conditions. verify the feedback winding settles to an acceptable limit for good line and load regulation. effect of fast (500 ns) versus slow (2 s) recovery diodes in clamp circuit on pulse grouping and output ripple. a slow reverse recovery diode reduces the feedback voltage ringing. the amplitude of ringing with a fast diode represents 8% error in figure 10. figure 9. rcd clamp, low power or low leakage inductance designs. rcd clamp with zener bleed. high power or high leakage inductance designs. figure 10. effect of clamp diode on feedback pin settling. clamp circuit (top). feedback pin voltage (bottom). c c1 r c1 r c2 d c1 pi-5107-110308 d c2 r c2 r c1 c c1 d c1 pi-5108-110308 c c1 r c1 r c2 d c1 pi-5107-110308 black trace: d c1 is a fr107 (fast type, trr = 500 ns) gray trace: d c1 is a 1n4007g (standard recovery, trr = 2 us) www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 9 lnk623-626 www.powerint.com figure 11. not pulse grouping (<5 consecutive switching cycles). pulse grouping (>5 consecutive switching cycles). top trace: drain waveform (200 v/div) bottom trace: output ripple voltage (50 mv/div) split screen with bottom screen zoom top trace: drain waveform (200 v/div) bottom trace: output ripple voltage (50 mv/div) clampless designs clampless designs rely solely on the drain node capacitance to limit the leakage inductance induced peak drain-to-source voltage. therefore the maximum ac input line voltage, the value of v or , the leakage inductance energy, (a function of leakage inductance and peak primary current), and the primary winding capacitance determine the peak drain voltage. with no signi? - cant dissipative element present, as is the case with an external clamp, the longer duration of the leakage inductance ringing can increase emi. the following requirements are recommended for a universal input or 230 vac only clampless design: 1. clampless designs should only be used for p o 5 w using a v or of 90 v 2. for designs with p o 5 w, a two-layer primary must be used to ensure adequate primary intra-winding capacitance in the range of 25 pf to 50 pf. a bias winding must be added to the transformer using a standard recovery recti? er diode (1n4003C 1n4007) to act as a clamp. this bias winding may also be used to externally power the device by connecting a resistor from the bias winding capacitor to the bypass pin. this inhibits the internal high-voltage current source, reducing device dissipation and no-load consumption. 3. for designs with p o >5 w, clampless designs are not practical and an external rcd or zener clamp should be used. 4. ensure that worst-case, high line, peak drain voltage is below the bv dss speci? cation of the internal mosfet and ideally 650 v to allow margin for design variation. v or (re? ected output voltage), is the secondary output plus output diode forward voltage drop that is re? ected to the primary via the turns ratio of the transformer during the diode conduction time. the v or adds to the dc bus voltage and the leakage spike to determine the peak drain voltage. pulse grouping pulse grouping is de? ned as 6 or more consecutive pulses followed by two or more timing state changes. the effect of pulse grouping is increased output voltage ripple. this is shown on the right of figure 11 where pulse grouping has caused an increase in the output ripple. to eliminate group pulsing verify that the feedback signal settles within 2.1 s from the turn off of the internal mosfet. a zener diode in the clamp circuit may be needed to achieve the desired settling time. if the settling time is satisfactory, then a rc network across r lower (r6) of the feedback resistors is necessary. the value of r (r5 in the figure 12) should be an order of magnitude greater than r lower and selected such that rc = 32 s where c is c5 in figure 12. quick design checklist as with any power supply design, all linkswitch-cv designs should be veri? ed on the bench to make sure that component speci? cations are not exceeded under worst-case conditions. figure 12. rc network across r bottom (r6) to reduce pulse grouping. pi-5268-110608 d s fb bp r3 6.34 k 7 1% r6 4.02 k 7 1% r4 6.2 k 7 c4 1 m f 50 v c5 680 pf 50 v c6 10 m f 50 v r5 47 k 7 1/8 w u1 lnk626pg linkswitch-cv d6 1n4148 5 4 2 top trace: drain waveform (200 v/div) bottom trace: output ripple voltage (50 mv/div) split screen with bottom screen zoom top trace: drain waveform (200 v/div) bottom trace: output ripple voltage (50 mv/div) www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 10 lnk623-626 www.powerint.com the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that peak v ds does not exceed 680 v at highest input voltage and maximum output power. 2. maximum drain current C at maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of trans- former saturation and excessive leading edge current spikes. linkswitch-cv has a leading edge blanking time of 215 ns to prevent premature termination of the on-cycle. verify that the leading edge current spike is below the allowed current limit envelope for the drain current waveform at the end of the 215 ns blanking period. 3. thermal check C at maximum output power, both minimum and maximum input voltage and maximum ambient tempera- ture; verify that temperature speci? cations are not exceeded for linkswitch-cv, transformer, output diodes and output capacitors. enough thermal margin should be allowed for the part-to-part variation of the r ds(on) of linkswitch-cv, as speci? ed in the data sheet. it is recommended that the maximum source pin temperature does not exceed 110 c. design tools up-to-date information on design tools can be found at the power integrations web site: www.powerint.com www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 11 lnk623-626 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise speci? ed) min typ max units control functions output frequency f osc t j = 25 c, v fb = v fbth lnk623/6 93 100 106 khz frequency jitter peak-peak jitter compared to average frequency, t j = 25 c 7 % ratio of output frequency at auto-rst f osc(ar) t j = 25 c relative to f osc (see note 3) 80 % maximum duty cycle dc max (note 2,3) t j = 25 c 54 % feedback pin voltage v fbth t j = 25 c see figure 15, c bp = 1 f lnk623-624p 1.815 1.840 1.865 v lnk623-624d 1.855 1.880 1.905 lnk625p, lnk625d 1.835 1.860 1.885 lnk626p, lnk626d 1.775 1.800 1.825 feedback pin voltage temperature coef? cient tc vfb -0.01 %/c feedback pin voltage at turn-off threshold v fb(ar) 1.45 v power coef? cient i 2 f i 2 f = i 2 limit(typ) f osc(typ) lnk623/6p t j = 25 c 0.9 i 2 fi 2 f 1.17 i 2 f a 2 hz i 2 f = i 2 limit(typ) f osc(typ) lnk623/6d t j = 25 c 0.9 i 2 fi 2 f 1.21 i 2 f absolute maximum ratings (1,4) drain voltage .................................. ......... ..............-0.3 v to 700 v drain peak current: lnk623 ......................... 400 (600) ma (4) lnk624 ......................... 400 (600) ma (4) lnk625 ..........................528 (790) ma (4) lnk626 ........................720 (1080) ma (4) peak negative pulsed drain current ................... ...... -100 ma (2) feedback voltage ................................................. ....... -0.3 v to 9 v feedback current ................................................. .............. 100 ma bypass pin voltage ..................................... ............. -0.3 v to 9 v storage temperature ...................................... ..... -65 c to 150 c operating junction temperature.........................-40 c to 150 c lead temperature (3) .................................................................260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. duration not to exceed 2 msec. 3. 1/16 in. from case for 5 seconds. 4. the higher peak drain current is allowed while the drain voltage is simultaneously less than 400 v. 5. maximum ratings speci? ed may be applied, one at a time without causing permanent damage to the product. exposure to absolute maximum ratings for extended periods of time may affect product reliability. thermal resistance thermal resistance: p package: ( ja ) .......................... ..........70 c/w (2) ; 60 c/w (3) ( jc ) (1) ............................................... ......... 11 c/w d package: ( ja .....................................100 c/w (2) ; 80 c/w (3) ( jc ) (1) .......................... ...........................30 c/w notes: 1. measured on pin 8 (source) close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 12 lnk623-626 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise speci? ed) min typ max units control functions (cont.) minimum switch on-time t on(min) (see note 3) 700 ns feedback pin sampling delay t fb (see figure 19) 2.35 2.55 2.75 s drain supply current i s1 fb voltage > v fbth 280 330 a i s2 fb voltage = v fbth -0.1, switch on-time = t on (mosfet switching at f osc ) lnk623/4 440 520 lnk625 480 560 lnk626 520 600 bypass pin charge current i ch1 v bp = 0 v lnk623/4 -5.0 -3.4 -1.8 ma lnk625/6 -7.0 -4.5 -2.0 i ch2 v bp = 4 v lnk623/4 -4.0 -2.3 -1.0 lnk625/6 -5.6 -3.2 -1.4 bypass pin voltage v bp 5.65 6.00 6.25 v bypass pin voltage hysteresis v bph 0.70 1.00 1.20 v bypass pin shunt voltage v shunt 6.2 6.5 6.8 v circuit protection current limit i limit lnk623 di/dt = 50 ma/ s , t j = 25 c 196 210 225 ma lnk624 di/dt = 60 ma/ s , t j = 25 c 233 250 268 lnk625 di/dt = 80 ma/ s , t j = 25 c 307 330 353 lnk626 di/dt = 110 ma/ s , t j = 25 c 419 450 482 leading edge blanking time t leb t j = 25 c (see note 3) 170 215 ns thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t sdh 60 c www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 13 lnk623-626 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c (unless otherwise speci? ed) min typ max units output on-state resistance r ds(on) lnk623 i d = 50 ma t j = 25 c 24 28 t j = 100 c 36 42 lnk624 i d = 50 ma t j = 25 c 24 28 t j = 100 c 36 42 lnk625 i d = 62 ma t j = 25 c 16 19 t j = 100 c 24 28 lnk626 i d = 82 ma t j = 25 c 9.6 11 t j = 100 c 14 17 off-state leakage i dss1 v ds = 560 v (see figure 20) t j = 125 c (see note 1) 50 a i dss2 v ds = 375 v (see figure 20) t j = 50 c 15 breakdown voltage bv dss t j = 25 c (see figure 20) 700 v drain supply voltage 50 v auto-restart on-time t ar-on v fb = 0 (see note 3) 200 ms auto-restart off-time t ar-off 2.5 s open-loop fb pin current threshold i ol (see note 3) -120 a open-loop on-time (see note 3) 90 s notes: 1. i dss1 is the worst case off state leakage speci? cation at 80% of bv dss and maximum operating junction temperature. i dss2 is a typical speci? cation under worst case application conditions (recti? ed 265 vac) for no-load consumption calculations. 2. when the duty cycle exceeds dc max the linkswitch-cv operates in on-time extension mode. 3. this parameter is derived from characterization. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 14 lnk623-626 www.powerint.com 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) frequency (normalized to 25 c) pi-5086-041008 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) feedback voltage (normalized to 25 c) pi-5089-040508 figure 13. output frequency vs, temperature. figure 14. feedback voltage vs, temperature. typical performance characteristics figure 15. breakdown vs. temperature. 1.1 1.0 0. 9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) b rea kd own v o l tage (normalized to 25 c) pi-2213-012301 drain voltage (v) drain c urrent (ma) 300 250 200 100 50 150 0 0 2 4 6 8 10 t case =25 c t case =100 c pi-5211-080708 lnk623 1.0 lnk624 1.0 lnk625 1.5 lnk626 2.5 scaling factors: drain voltage (v) drain capacitance (pf) pi-5201-07170 8 0 100 200 300 400 500 600 1 10 100 1000 lnk623 1.0 lnk624 1.0 lnk625 1.5 lnk626 2.5 scaling factors: 50 30 40 10 20 0 0 200 400 60 0 drain voltage (v) power (mw) pi - 5212 - 0 8 070 8 lnk623 1.0 lnk624 1.0 lnk625 1.5 lnk626 2.5 scaling factors: figure 16. output characteristic. figure 17. c oss vs. drain voltage. figure 18. drain capacitance power. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 15 lnk623-626 www.powerint.com figure 19. test set-up for feedback pin measurements. pi-5202-073108 6.2 v 500 7 1) raise v bp voltage from 0 v to 6.2 v, down to 4.5 v, up to 6.2 v 2) raise v in until cycle skipping occurs at v out to measure v fbth 3) apply 1.6 v at v in and measure t fb delay from start of cycle falling edge to the next falling edge s d s s fb s 10 m f bp + 2 v + v in + v out linkswitch-cv figure 20. test set-up for leakage and breakdown tests. pi-5203-071408 16 v to measure bv dss , i dss1 , and i dss2 follow these steps: 1) close s1, open s2 2) power-up v in source (16 v) 3) open s1, close s2 4) measure i/v characteristics of drain pin using the curve tracer s d s s fb s .1 m f 1 m f bp v in linkswitch-cv 5 m f 50 k 7 + curve tracer s1 s2 4 k 7 10 k 7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 16 lnk623-626 www.powerint.com notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 3 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body. 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 seating plane -d- -t- p08c dip-8c (p package) pi-3 9 33-101507 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum www.datasheet.co.kr datasheet pdf - http://www..net/
rev. e 09/09 17 lnk623-626 www.powerint.com part ordering information ? linkswitch product family ? cv series number ? package identi? er p plastic dip d plastic so-8 ? package material g green: halogen free and rohs compliant ? tape & reel and other options blank standard con? gurations tl tape & reel, 2.5 k pcs for d package. not available for p package. lnk 625 d g - tl pi-4526-040207 d07c so-8c 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal burr. 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h o 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc seating plane 0.25 (0.010) 0.17 (0.007) detail a detail a c seating plane pin 1 id b 4 + + + 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions + www.datasheet.co.kr datasheet pdf - http://www..net/
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integra tions. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a licens e under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustai ns life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in s igni? cant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2008, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date b release data sheet 11/08 c correction made to figure 5 12/08 d introduced max current limit when v drain is below 400 v 07/09 e introduced lnk626dg 09/09 www.datasheet.co.kr datasheet pdf - http://www..net/

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